Data signals are commonly transmitted and received in conjunction with associated clock signals. A clock signal allows a receiver to extract data from a data signal by defining the bit-cell boundaries of the data signal. Clock signals are controlled by clocking circuits that are associated with data-carrying communication links.
A clocking circuit that is associated with a communication link is ideally capable of supporting any data rate that can be supported by the communication link and its associated transmitter and receiver. However, the speed and performance of a communication link are often limited by its clocking circuit. More specifically, a communication link may be prevented from carrying data at a particular rate because an associated clocking circuit is unable to generate clocking signals that define bit-cell lengths required by the data rate. Consequently, circuit designers desire clocking systems that support data rates that are greater than those supported by current clocking systems.